A critical performance feature in any data processing system is the speed at which the CPU can complete an access (read operation or write operation) to electronic memory. The faster data is transferred between the CPU and memory, the better the performance of the processing system. One way data can be transferred more rapidly between the CPU and memory is by increasing the width of the data bus portion of the CPU local bus from, for example, 16 bits to 32 bits, 64 bits or 72 bits. In this way, data words of different sizes up to the maximum size data word for the system can be transferred across the data bus in a single operation.
However, expanding the size of the data bus requires the addition of more memory chips and increases the amount of board space required. Thus, the overall size, complexity and cost of the system are increased. As a result, it is currently preferable to read/write large data words that exceed the data bus width in sequential steps rather than to tailor the width of the data bus to the largest expected data word. For example, in a processing system having a 16 bit data bus, 16-bit words are stored or retrieved in a single memory access cycle for ordinary processor instructions. However, during double-precision instruction operations, a 32-bit word is stored or retrieved from memory in two memory access cycles.
One widely used electronic memory device is the dynamic random access memory (DRAM). Conventional electronic memories, including DRAMs, are of fixed I/O width. These devices store data in an array of N by M bits of storage, where N is the number of rows and M is the number of columns in the array. A K-bit location in memory is accessed using a row address, which accesses one row (containing M bits) out of N possible rows, and a column address, which accesses K columns (containing 1 bit each) out of the M columns (bits) in the accessed row. Row and column addresses are usually multiplexed through a single address port in two portions in order to minimize the number of pins required for interfacing with the address bus.
For example, a 256K.times.16 bit DRAM is a 4 megabit DRAM configured to allow access through a 16-pin data bus to a 16-bit location during each random access (one row and one column address). The 256K 16-bit data words require an 18-bit address in order to be separately addressable. Typically, a 9-pin address port is used. During a typical DRAM read or write operation, nine row address bits are first sent to the DRAM address port and latched in with a row address strobe (RAS). Nine column address bits are next sent to the DRAM address lines and latched in with a column address strobe (CAS).
Row address bits A.sub.0 -A.sub.8, are sent to a row decoder which accesses one of 512 rows. Each row contains 8192 columns (i.e., 512.times.16 columns) and each column contains one storage cell (bit). Column address bits A.sub.9 -A.sub.17 are sent to a column decoder which accesses one of 512 16-bit storage locations (words) within the accessed row, each storage location corresponding to a group of 16 columns. Depending on whether a read or write operation is being performed, 16 bits of data are either read from or written into the 16 storage cells accessed by the row and column address bits.
In the case where a 32-bit data word is being stored or retrieved, a second sequential column address must also be sent to the DRAM and latched in with a second CAS signal. A second 16 bits of data are then stored or retrieved. If the last column in the accessed row had been reached after the first CAS signal, a new row address and RAS signal would also have to be provided. The substantial drawback to this memory access scheme is that multiple memory addresses are required for data words that are larger than the data I/O width of the electronic memory. This necessarily requires the processor to maintain extra address "overhead" in order to access the larger data words stored in system memory and to prevent the second half of the larger words from being accidently overwritten.
There is therefore a need for improved memory circuits and processing systems using the improved memory circuits that can more easily access large data words in system memory. In particular, there is a need for processing systems and memory devices that can more easily access large data words in system memory by configuring the data I/O width of the memory devices "on the fly."